1. Field of the Invention
The present invention relates to an electronic component built-in substrate and a method of manufacturing the same and, more particularly, an electronic component built-in substrate having such a structure that an electronic component is mounted on the substrate in a state that the electronic component is embedded in an insulating layer and a method of manufacturing the same.
2. Description of the Related Art
In the prior art, there is the electronic component built-in substrate having such a structure that an electronic component is mounted on the substrate in a state that the electronic component is embedded in an insulating layer. As shown in FIG. 1, in the electronic component built-in substrate in the prior art, through holes 100xpassing through a core substrate 100 are provided in this core substrate, and a through-hole plating layer 110 is formed on inner surfaces of the through holes 100x. A resin 130 is filled in the through holes 100x. A first wiring layer 120 is formed on both surface sides of the core substrate 100 respectively. The first wiring layers 120 on both surface sides are connected mutually via the through-hole plating layers 110.
Also, a semiconductor chip 200 is mounted on the first wiring layer 120 on the upper surface side of the core substrate 100 such that its connection electrodes 200a are directed upward. A first insulating layer 140 and a second insulating layer 160 are formed around the semiconductor chip 200, so that the semiconductor chip 200 is buried in the first insulating layer 140 and the second insulating layer 160. First via holes V1 each having a depth reaching the first wiring layer 120 are formed in the first and second insulating layers 140, 160. Also, second via holes V2 each having a depth reaching the connection electrode 200a of the semiconductor chip 200 are formed in the second insulating layer 160. Also, a second wiring layer 180 connected to the first wiring layer 120 via the first via holes V1 and connected to the connection electrodes 200a of the semiconductor chip 200 via the second via holes V2 is formed on the second insulating layer 160.
Also, the first and second insulating layers 140, 160 are formed similarly on the first wiring layer 120 on the lower surface side of the core substrate 100, and the first via holes V1 each having a depth reaching the first wiring layer 120 are formed. Also, the second wiring layer 180 connected to the first wiring layer 120 via the first via holes V1 is formed on the second insulating layer 160.
Also, a third insulating layer 210 in which third via holes V3 are provided is formed on the second wiring layer 180 on both surface sides of the core substrate 100 respectively. Also, a third wiring layer 220 connected to the second wiring layer 180 via the third via holes V3 is formed on the third insulating layer 210 on both surface sides of the core substrate 100 respectively. Also, a solder resist film 240 in which opening portions 240x are provided on connection portions of the third wiring layer 220 is formed on the third wiring layer 220 on both surface sides of the core substrate 100 respectively.
The such electronic component built-in substrate in which the electronic component is mounted on the substrate in a state that the electronic component is embedded in the insulating layer is set forth in Patent Literature 1 (Patent Application Publication (KOKAI) 2005-327984), for example.
Also, in Patent Literature 2 (Patent Application Publication (KOKAI) 2002-314245), it is set forth that the vias are formed by inserting a copper ball into the through holes in the core substrate and then the plural-layered core substrate whose vias are connected electrically is manufactured by joining plural sheets of such core substrates together.
In the electronic component built-in substrate in the prior art, the first and second insulating layers 140, 160 in which the semiconductor chip 200 is embedded must be formed to have a film thickness enough to cover the semiconductor chip 200. Therefore, the film thickness of these insulating layers must be set considerably thicker (twice or more) than that of the ordinary interlayer insulating layer (in FIG. 1, the third insulating layer 210) in which the semiconductor chip is not embedded.
For this reason, the first via holes V1 formed in the first and second insulating layers 140, 160 in which the semiconductor chip 200 is embedded, to reach the first wiring layer 120, are larger in depth and diameter than the via holes formed in the ordinary interlayer insulating layer.
As a result, in FIG. 1, in fact, it is extremely difficult from a cost point of view to fill perfectly a metal in the first via holes V1, the volume (diameter and depth) of which is considerable large, by the electroplating. Only a metal layer is formed on inner walls of the first via holes V1, and thus the cavities often remain in the inside of the holes.
When the cavities exist in the insides of the first via holes V1, it is difficult to place the via hole just on the first via holes V1. Therefore, as shown in FIG. 1, the third via holes V3 must be shifted and placed on the second wiring layer 180 that extends laterally from the first via holes V1. As a result, such a problem exists that the stacked via structure effective in forming the multi-layered wiring with high density cannot be employed.